芯片验证水平测评

花几分钟的时间，测试一下你的真实水平吧！看你是否达到芯片验证工程师入门水平，现在我们就马上开始吧！

Q1:姓名

填空1

Q2:手机

填空1

Q3:1、What is a virtual interface? 【单选题】

A. An Interface containing a virtual class

B. A handle to a physical interface

C. A Module containing a handle to physical interface

D. A Class containing a handle to physical interface

Q4:2、When will this immediate assertion pass? Moduletest ; … always @ (posedge clock) LABEI_ WR_ RD: assert ( write_ enable read_ enable) ; … 【单选题】

A. When both write_ enable and read_enable are true

B. When write_ enable is true and read_ enable is false

C. When write_ enable is false and read_ enable is true

D. All of the above

Q5:3、What is the difference between get( ) and peek( ) methods in mailbox? 【单选题】

A. peek( ) is non-blocking and get( ) is blocking

B. Both are blocking, while get( ) removes the item and peek( ) makes a copy from the mailbox

C. get( ) is non-blocking and peek( ) is blocking

D.Both are non-blocking, while get( ) removes the item and peek( ) makes a copy from the mailbox

Q6:4、What is wrong with this code? module test; class ex; int y; endclass ex ex_h; initial begin ex_h . y = 10; end endmodule 【单选题】

A. null object access error

B. class handle is declared outside the initial block

C. constructor is not present in the class definition

D. nothing is wrong in the code

Q7:5、How can you disable randomization of a class property?(select all that apply) 【单选题】

A. set rand_mode to 0

B. Avoid Randomization

C. constrain the property to 0

D. set constraint_ mode to 0

Q8:6、What will be the value of data after randomization? rand bit [7 :0] data; constraint data_ c { ! (data inside { [50: 60]} ;) ;} 【单选题】

A. Between 50 and 60

B. Less than 50 or greater than 60

C. Results in Error

D. Greater than 50 or less than 60

Q9:7、Which of the following keyword allows you to specify relative probability constraints for randomized values? 【单选题】

A. dist

B. probability

C. randcase

D. randc

Q10:8、How can you pass a value of 30 to variable z while invoking the below write task?(select all which apply) Task write (int x=10，int y=20，int z); … endtask 【多选题】

A. write(.z(30).x(30));

B. write(30);

C. write(,30,30);

D. write(10,30,);

Q11:9、Which of the following variables are 4 state? (select all that apply) 【多选题】

A. int sig;

B. shortint one;

C. wire enable;

D. logic valid;

Q12:10、Is the following definition of semaphore (with name acces_ mem and with number of keys of 10) correct? semaphore acces_mem = new(10) 【单选题】

A. Yes

B. No

Q13:11、What is the default verbosity? 【单选题】

A. UVM_ NONE

B. UVM_ LOW

C. UVM_ MEDIUM

D. UVM_ HIGH

C. UVM_ FULL

Q14:12、Which of the following phase methods are tasks? 【多选题】

A. build_ phase

B. report phase

C. start_ of simulation_ phase

D. main_ phase

E. check _phase

F. extract phase

G. run_ .phase

H. connect _phase

I. end. of elaboration_ phase

Q15:13、Which of the following UVC component classes can be type parameterized for a data item? 【多选题】

A. UVC top level environment

B. Agent

C. Sequencer

D. Driver

E. Monitor

Q16:14、The method call get next item( ) opens a sequence transaction in a driver, but what closes the transaction? 【单选题】

A. Method call send_ to_ dut ()

B. Method call item done ()

C. Next call toget_ next_ item()

D. Method call item_ close ()

E. Method call done_ item ()

Q17:15、In this declaration, why am I not using the factory create() method? uvm_ _analysis_ _port # (mypacket) pkt_ _out = new(pkt_ out, this) 【单选题】

A.It is bad practice - you should always use the factory

B.TLM object do not have utility macros so can never be used with the factory

C.TLM objects are automatically factory enabled so a create is redundant

D.Factory type overrides would break TLM object method dependencies

Q18:16、Which is the UVC component primarily responsible for coverage and checking? 【单选题】

A.UVC top level environment

B.Agent

C.Driver

D.Sequencer

E.Monitor

Q19:17、From which UVM class do you extend a data stimulus item declaration? 【单选题】

A.uvm_ sequence_ item

B.uvm_ object

C.uvm_ component

D.uvm_ sequence

E.uvm data item

Q20:18、Which of the following sequence macros are used in multichannel sequences to directly execute a UVC sequence? 【单选题】

A.uvm_ do

B. uvm_ _do_ _on

C. uvm_ rand_ send_ with

D. uvm_ _do_ with

E.uvm_ _do_ on_ with

Q21:19、Which phase method must always have a super call for configuration? 【单选题】

A. build_ .phase

B. connect_ phase

C. end_ of. _elaboration. _phase

D. start_ of_ _simulation_ .phase

E. run_ _phase

F.extract_ .phase

G.check_ phase

H.report_ phase

Q22:20、What is the verbosity of a uvm_ error report? 【单选题】

A. UVM_ NONE

B. UVM_ LOW

C. UVM_ MEDIUM

D. UVM_ HIGH

E. UVM_ FULL

芯片验证水平测评

关于

1年前

更新

频次

题目数

有问题？问问AI帮你修改改主题：如咖啡问卷改为奶茶问卷